Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot generally be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM typically comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modern personal computers (PCs) and processor based systems have their basic input/output system (BIOS) code stored on a Flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a Flash BIOS. In a PC or processor based system, the memory that stores the BIOS code is typically called the “boot memory”, as it is usually the first code that the processor executes upon reset or power up. The code the boot memory contains initializes the system, sets up basic environmental variables and interrupt vectors, initializes peripherals, and, finally, loads and begins execution of the operating system (OS) or main executable of the PC or processor based system.
A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU's bus and is capable of running at 100 MHZ, 133 MHZ, 166 MHZ, or 200 MHZ, about three or more times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. An extended form of SDRAM that can transfer a data value on the rising and falling edge of the clock signal is called double data rate SDRAM (DDR SDRAM, or simply, DDR). SDRAM's can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory. A synchronous Flash memory (Also referred to as a SyncFlash) has been designed that allows for a non-volatile memory device with an SDRAM interface. Although knowledge of the function and internal structure of a synchronous Flash memory is not essential to understanding the present invention, a detailed discussion is included in U.S. patent application Ser. No. 09/627,682 filed Jul. 28, 2000 and titled, “Synchronous Flash Memory,” which is commonly assigned and incorporated by reference.
In general, the goal of synchronous Flash is to mimic the architecture of SDRAM. It has an SDRAM interface which is compatible to SDRAM for read operation to the synchronous Flash memory. Programming, erasing, block protection and other Flash specific function differ from SDRAM and are performed with a three cycle SDRAM command sequence.
Generally, addressing in conventional memory subsystems is accomplished by a combination of the internal address decoding of individual memory devices, external address decoding, and/or chip select lines. Each memory device typically contains its own internal address decoding that decodes the requested memory access placed on the address lines of the memory device and allows access to the requested memory data words of the internal memory array that are being addressed. External addressing that places parts or all of the internal address range of a memory device into the physical address range of the memory subsystem is typically done by external decoders and/or by the utilization of chip select lines. External decoders are similar to and extend the internal decoders of the memory device(s). They decode the extended address that the memory subsystem receives for an individual memory access that is typically beyond the full address range of an individual memory device. They also map the individual memory device or portion of an individual memory device address range into the physical address range of the memory subsystem. Chip select lines can also be used to map memory devices into the physical address range of the memory subsystem by selectively activating one or more individual memory devices for access as part of the address range of the memory subsystem in isolation from other addressable on the same memory interface bus. In this manner many memory devices can share the same address, control, and data lines in the memory subsystem. Chip select lines can also be utilized in conjunction with external address decoders in a system if desired. However, in many cases a memory subsystem utilizes only the chip select lines to map individual memory device address ranges or portions of address ranges into the physical memory map that the memory subsystem presents. This allows the memory subsystem to utilize more complex decoding schemes without hardwired external decoding that can be programmable and/or change over time, such as with a virtual memory (VM) system or a memory management unit (MMU).
Memory interfaces/busses that utilize SDRAM's typically assign chip selects and/or physical memory address ranges in a manner that is based on the physical memory slot that the memory device is inserted into and not the type of memory being inserted/utilized or its contents. For example, a SDRAM memory module inserted into slot 0 of a SDRAM memory subsystem will be assigned to chip select 0 and chip select 1, the SDRAM memory module in slot 1 with be assigned chip selects 2 and 3, and so on. Furthermore, the number of physical SDRAM memory slots and their placement order is not generally specified in the SDRAM specification, so that the physical configuration and ordering of a SDRAM memory subsystem's SDRAM memory slots can differ from system to system. Because of this, a SDRAM memory that is placed into a physical SDRAM memory slot of the memory system cannot generally be guaranteed a specific memory address and chip select(s).
A problem with this is that to begin operation upon reset/power up, a PC or processor based system needs a method that is predictable to find the boot memory device. This has generally been achieved in the prior art by the placement of the boot memory device in a specific physical memory address range or by associating the boot memory with a specific chip select. For example, many PC's and other processor based systems utilize a boot memory that has a fixed memory address and/or a fixed “boot memory” chip select signal that activates the boot memory for access from the processor or memory controller (referred to herein as a memory controller). It is difficult to utilize a synchronous Flash memory device as such a boot memory device, however, because of the generally unpredictable assignment of chip select and physical memory address of a SDRAM memory slot of a SDRAM memory subsystem. The boot memory therefore cannot be guaranteed a specific chip select and/or address space without special consideration being taken, making synchronous Flash memories difficult to utilize as a boot memory device.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a synchronous Flash memory device that can operate as a boot memory device in a SDRAM memory system without the assignment of a specific chip select or memory range.